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M95M01-R
1 Mbit serial SPI bus EEPROM with high speed clock
Features

Compatible with SPI bus serial interface (Positive Clock SPI modes) Schmitt trigger inputs for enhanced noise margin Single supply voltage: 1.8 V to 5.5 V High speed - 5 MHz clock rate - 5 ms Write time Status Register Hardware Protection of the Status Register Byte and Page Write (up to 256 bytes) Self-timed programming cycle Adjustable size read-only EEPROM area Enhanced ESD Protection More than 1 000 000 Write cycles More than 40-year data retention Packages - ECOPACK(R) (RoHS compliant)
SO8W (MW) 208 mils width SO8N (MN) 150 mils width

January 2008
Rev 5
1/40
www.st.com 1
Contents
M95M01-R
Contents
1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4
Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1.1 4.1.2 4.1.3 4.1.4 Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2 4.3 4.4 4.5
Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . . . 13 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5 6
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1 6.2 6.3 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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M95M01-R 6.3.2 6.3.3 6.3.4
Contents WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.4 6.5 6.6
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7 8
ECC (error correction code) and write cycling . . . . . . . . . . . . . . . . . . . 27 Power-up and delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.1 8.2 Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
9 10 11 12 13
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
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List of tables
M95M01-R
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Address range bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 AC characteristics (VCC 2.5 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 AC characteristics (VCC < 2.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 SO8 narrow - 8 lead plastic small outline, 150 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 SO8W - 8 lead plastic small outline, 208 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Available M95M01-R products (package, voltage range, temperature grade) . . . . . . . . . . 38 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
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M95M01-R
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 SO connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Write Disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Write Status Register (WRSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 SO8 narrow - 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . 35 SO8W - 8 lead plastic small outline, 208 mils body width, package outline. . . . . . . . . . . . 36
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Description
M95M01-R
1
Description
The M95M01-R is an electrically erasable programmable memory (EEPROM) device. It is accessed by a high speed SPI-compatible bus. The memory array is organized as 131 072 x 8 bit. It can also be seen as 512 pages of 256 bytes each. The device is accessed by a simple serial interface that is SPI-compatible. The bus signals are C, D and Q, as shown in Table 1 and Figure 1. The device is selected when Chip Select (S) is taken Low. Communications with the device can be interrupted using Hold (HOLD). In order to meet environmental requirements, ST offers the M95M01-R in ECOPACK(R) packages. ECOPACK(R) packages are Lead-free and RoHS compliant. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 1. Logic diagram
VCC
D C S W HOLD M95xxx
Q
VSS
AI01789C
Table 1.
Signal names
Signal name Function Serial Clock Serial Data Input Serial Data Output Chip Select Write Protect Hold Supply voltage Ground Input Input Output Input Input Input Direction
C D Q S W HOLD VCC VSS
6/40
M95M01-R Figure 2. SO connections
M95xxx S Q W VSS 1 2 3 4 8 7 6 5
AI01790D
Description
VCC HOLD C D
1. See Section 11: Package mechanical data for package dimensions, and how to identify pin-1.
7/40
Signal description
M95M01-R
2
Signal description
During all operations, VCC must be held stable and within the specified valid range: VCC(min) to VCC(max). All of the input and output signals must be held High or Low (according to voltages of VIH, VOH, VIL or VOL, as specified in Table 11). These signals are described next.
2.1
Serial Data Output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C).
2.2
Serial Data Input (D)
This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be written. Values are latched on the rising edge of Serial Clock (C).
2.3
Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock (C).
2.4
Chip Select (S)
When this input signal is High, the device is deselected and Serial Data Output (Q) is at high impedance. Unless an internal Write cycle is in progress, the device will be in the Standby Power mode. Driving Chip Select (S) Low selects the device, placing it in the Active Power mode. After Power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction.
2.5
Hold (HOLD)
The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device. During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don't Care. To start the Hold condition, the device must be selected, with Chip Select (S) driven Low.
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M95M01-R
Signal description
2.6
Write Protect (W)
The main purpose of this input signal is to freeze the size of the area of memory that is protected against Write instructions (as specified by the values in the BP1 and BP0 bits of the Status Register). This pin must be driven either High or Low, and must be stable during all write instructions.
2.7
VCC supply voltage
VCC is the supply voltage.
2.8
VSS ground
VSS is the reference for the VCC supply voltage.
9/40
Connecting to the SPI bus
M95M01-R
3
Connecting to the SPI bus
These devices are fully compatible with the SPI protocol. All instructions, addresses and input data bytes are shifted in to the device, most significant bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C) after Chip Select (S) goes Low. All output data bytes are shifted out of the device, most significant bit first. The Serial Data Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction (such as the Read from Memory Array and Read Status Register instructions) have been clocked into the device. Figure 3. Bus master and memory devices on the SPI bus
VSS VCC R SDO SPI Interface with (CPOL, CPHA) = (0, 0) or (1, 1) SDI SCK CQD SPI Bus Master R CS3 CS2 CS1 S W HOLD S W HOLD S W HOLD SPI Memory Device VCC VSS R SPI Memory Device CQD VCC VSS R SPI Memory Device CQD VCC VSS
AI12836b
1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
Figure 3 shows an example of three memory devices connected to an MCU, on an SPI bus. Only one device is selected at a time, so only one device drives the Serial Data Output (Q) line at a time, the other devices are high impedance. The pull-up resistor R (represented in Figure 3) ensures that no device is selected if the Bus Master leaves the S line in the high impedance state. In applications where the Bus Master might enter a state where all inputs/outputs SPI lines are in high impedance at the same time (for example, if the Bus Master is reset during the transmission of an instruction), the clock line (C) must be connected to an external pulldown resistor so that, if all inputs/outputs become high impedance, the C line is pulled Low (while the S line is pulled High). This ensures that S and C do not become High at the same time, and so, that the tSHCH requirement is met.
10/40
M95M01-R
Connecting to the SPI bus
3.1
SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes:

CPOL=0, CPHA=0 CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C). The difference between the two modes, as shown in Figure 4, is the clock polarity when the bus master is in Standby mode and not transferring data:

C remains at 0 for (CPOL=0, CPHA=0) C remains at 1 for (CPOL=1, CPHA=1) SPI modes supported
Figure 4.
CPOL CPHA C
0
0
1
1
C
D
MSB
Q
MSB
AI01438B
11/40
Operating features
M95M01-R
4
4.1
4.1.1
Operating features
Supply voltage (VCC)
Operating supply voltage VCC
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Table 8.). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (tW).
4.1.2
Power-up conditions
When the power supply is turned on, VCC rises continuously from VSS to VCC. During this time, the Chip Select (S) line is not allowed to float but should follow the VCC voltage, it is therefore recommended to connect the S line to VCC via a suitable pull-up resistor. In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edge sensitive as well as level sensitive: after power-up, the device does not become selected until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select (S) must have been High, prior to going Low to start the first operation. The VCC rise time must not vary faster than 1 V/s.
4.1.3
Device reset
In order to prevent inadvertent Write operations during power-up (continuous rise of VCC), a power on reset (POR) circuit is included. At Power-up, the device does not respond to any instruction until VCC has reached the power on reset threshold voltage (this threshold is lower than the minimum VCC operating voltage defined in Table 8). When VCC has passed the POR threshold, the device is reset and in the following state:

Standby Power mode deselected (at next Power-up, a falling edge is required on Chip Select (S) before any instructions can be started) not in the Hold condition Status Register: - - the Write Enable Latch (WEL) is reset to 0 Write In Progress (WIP) is reset to 0. The SRWD, BP1 and BP0 bits of the Status Register are unchanged from the previous power-down (they are non-volatile bits)
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M95M01-R
Operating features
4.1.4
Power-down
At Power-down (continuous decrease in VCC), as soon as VCC drops from the normal operating voltage to below the power on reset threshold voltage, the device stops responding to any instruction sent to it. During Power-down, the device must be deselected (Chip Select (S) should be allowed to follow the voltage applied on VCC) and in Standby Power mode (that is there should be no internal Write cycle in progress).
4.2
Active Power and Standby Power modes
When Chip Select (S) is Low, the device is selected, and in the Active Power mode. The device consumes ICC, as specified in Table 11. When Chip Select (S) is High, the device is deselected. If a Write cycle is not currently in progress, the device then goes in to the Standby Power mode, and the device consumption drops to ICC1.
4.3
Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don't Care. To enter the Hold condition, the device must be selected, with Chip Select (S) Low. Normally, the device is kept selected, for the whole duration of the Hold condition. Deselecting the device while it is in the Hold condition, has the effect of resetting the state of the device, and this mechanism can be used if it is required to reset any processes that had been in progress. The Hold condition starts when the Hold (HOLD) signal is driven Low at the same time as Serial Clock (C) already being Low (as shown in Figure 5). The Hold condition ends when the Hold (HOLD) signal is driven High at the same time as Serial Clock (C) already being Low. Figure 5 also shows what happens if the rising and falling edges are not timed to coincide with Serial Clock (C) being Low.
13/40
Operating features Figure 5. Hold condition activation
M95M01-R
C
HOLD
Hold Condition
Hold Condition
AI02029D
4.4
Status Register
Figure 6 shows the position of the Status Register in the control logic of the device. The Status Register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. See Section 6.3: Read Status Register (RDSR) for a detailed description of the Status Register bits
4.5
Data protection and protocol control
Non-volatile memory devices can be used in environments that are particularly noisy, and within applications that could experience problems if memory bytes are corrupted. Consequently, the device features the following data protection mechanisms:

Write and Write Status Register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events: - - - - Power-up Write Disable (WRDI) instruction completion Write Status Register (WRSR) instruction completion Write (WRITE) instruction completion

The Block Protect (BP1, BP0) bits in the Status Register allow part of the memory to be configured as read-only. The Write Protect (W) signal allows the Block Protect (BP1, BP0) bits of the Status Register to be protected.
For any instruction to be accepted, and executed, Chip Select (S) must be driven High after the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising edge of Serial Clock (C). Two points need to be noted in the previous sentence:
The `last bit of the instruction' can be the eighth bit of the instruction code, or the eighth bit of a data byte, depending on the instruction (except for Read Status Register (RDSR) and Read (READ) instructions). The `next rising edge of Serial Clock (C)' might (or might not) be the next bus transaction for some other device on the SPI bus.
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M95M01-R Table 2. Write-protected block size
Status Register bits Protected block BP1 0 0 1 1 BP0 0 1 0 1 none Upper quarter Upper half Whole memory
Operating features
Array addresses protected none 1 8000h - 1 FFFFh 1 0000h - 1 FFFFh 0 0000h - 1 FFFFh
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Memory organization
M95M01-R
5
Memory organization
The memory is organized as shown in Figure 6. Figure 6.
HOLD W S C D Q Control Logic
Block diagram
High Voltage Generator
I/O Shift Register
Address Register and Counter
Data Register Status Register
Size of the Read only EEPROM area
Y Decoder
1 Page
X Decoder
AI01272C
16/40
M95M01-R
Instructions
6
Instructions
Each instruction starts with a single-byte code, as summarized in Table 3. If an invalid instruction is sent (one not contained in Table 3), the device automatically deselects itself. Table 3. Instruction set
Description Write Enable Write Disable Read Status Register Write Status Register Read from Memory Array Write to Memory Array Instruction format 0000 0110 0000 0100 0000 0101 0000 0001 0000 0011 0000 0010
Instruction WREN WRDI RDSR WRSR READ WRITE
6.1
Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction. The only way to do this is to send a Write Enable instruction to the device. As shown in Figure 7, to send this instruction to the device, Chip Select (S) is driven Low, and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven High. Figure 7. Write Enable (WREN) sequence
S 0 C Instruction D High Impedance Q
AI02281E
1
2
3
4
5
6
7
17/40
Instructions
M95M01-R
6.2
Write Disable (WRDI)
One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction to the device. As shown in Figure 8, to send this instruction to the device, Chip Select (S) is driven Low, and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven High. The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:

Power-up WRDI instruction execution WRSR instruction completion WRITE instruction completion. Write Disable (WRDI) sequence
Figure 8.
S 0 C Instruction D High Impedance Q
AI03750D
1
2
3
4
5
6
7
18/40
M95M01-R
Instructions
6.3
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Write or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible to read the Status Register continuously, as shown in Figure 9. The status and control bits of the Status Register are as follows:
6.3.1
WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress.
6.3.2
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write or Write Status Register instruction is accepted.
6.3.3
BP1, BP0 bits
The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Write instructions. These bits are written with the Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 4) becomes protected against Write (WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set.
6.3.4
SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W) signal allow the device to be put in the Hardware Protected mode (when the Status Register Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven Low). In this mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for execution. Table 4.
b7 SRWD 0 0 0 BP1 BP0 WEL
Status Register format
b0 WIP
Status Register Write Protect Block Protect Bits Write Enable Latch Bit Write In Progress Bit
19/40
Instructions Figure 9.
S 0 C Instruction D Status Register Out High Impedance Q 7 MSB 6 5 4 3 2 1 0 7 MSB 6 5 4 3 2 1 0 Status Register Out 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
M95M01-R Read Status Register (RDSR) sequence
7
AI02031E
20/40
M95M01-R
Instructions
6.4
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write Enable Latch (WEL). The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) Low, followed by the instruction code and the data byte on Serial Data Input (D). The instruction sequence is shown in Figure 10. The Write Status Register (WRSR) instruction has no effect on b6, b5, b4, b1 and b0 of the Status Register. b6, b5 and b4 are always read as 0. Chip Select (S) must be driven High after the rising edge of Serial Clock (C) that latches in the eighth bit of the data byte, and before the next rising edge of Serial Clock (C). Otherwise, the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Write Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset. Figure 10. Write Status Register (WRSR) sequence
S 0 C Instruction Status Register In 7 High Impedance Q
AI02282D
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
D
6
5
4
3
2
1
0
MSB
21/40
Instructions Table 5. Protection modes
Mode Write Protection of the Status Register Memory content Protected area(1)
M95M01-R
W SRWD Signal Bit 1 0 1 0 0 1
Unprotected area(1)
Status Register is Writable Software (if the WREN instruction Protected has set the WEL bit) Write Protected (SPM) The values in the BP1 and BP0 bits can be changed Status Register is Hardware Hardware write protected Protected The values in the BP1 and Write Protected (HPM) BP0 bits cannot be changed
Ready to accept Write instructions
0
1
Ready to accept Write instructions
1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 5.
The Write Status Register (WRSR) instruction allows the user to change the values of the Block Protect (BP1, BP0) bits, to define the size of the area that is to be treated as readonly, as defined in Table 4. The Write Status Register (WRSR) instruction also allows the user to set or reset the Status Register Write Disable (SRWD) bit in accordance with the Write Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W) signal allow the device to be put in the Hardware Protected Mode (HPM). The Write Status Register (WRSR) instruction is not executed once the Hardware Protected Mode (HPM) is entered. The contents of the Status Register Write Disable (SRWD) and Block Protect (BP1, BP0) bits are frozen at their current values from just before the start of the execution of Write Status Register (WRSR) instruction. The new, updated, values take effect at the moment of completion of the execution of Write Status Register (WRSR) instruction. The protection features of the device are summarized in Table 2. When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial delivery state), it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless of the whether Write Protect (W) is driven High or Low. When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two cases need to be considered, depending on the state of Write Protect (W):
If Write Protect (W) is driven High, it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. If Write Protect (W) is driven Low, it is not possible to write to the Status Register even if the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. (Attempts to write to the Status Register are rejected, and are not accepted for execution). As a consequence, all the data bytes in the memory area that are software protected (SPM) by the Block Protect (BP1, BP0) bits of the Status Register, are also hardware protected against data modification.
22/40
M95M01-R
Instructions Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be entered:

by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W) Low or by driving Write Protect (W) Low after setting the Status Register Write Disable (SRWD) bit.
The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write Protect (W) High. If Write Protect (W) is permanently tied High, the Hardware Protected Mode (HPM) can never be activated, and only the Software Protected Mode (SPM), using the Block Protect (BP1, BP0) bits of the Status Register, can be used.
23/40
Instructions
M95M01-R
6.5
Read from Memory Array (READ)
As shown in Figure 11, to send this instruction to the device, Chip Select (S) is first driven Low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data Input (D). The address is loaded into an internal address register, and the byte of data at that address is shifted out, on Serial Data Output (Q). If Chip Select (S) continues to be driven Low, the internal address register is automatically incremented, and the byte of data at the new address is shifted out. When the highest address is reached, the address counter rolls over to zero, allowing the Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a single READ instruction. The Read cycle is terminated by driving Chip Select (S) High. The rising edge of the Chip Select (S) signal can occur at any time during the cycle. The first byte addressed can be any byte within any page. The instruction is not accepted, and is not executed, if a Write cycle is currently in progress. Figure 11. Read from Memory Array (READ) sequence
S 0 C Instruction 24-bit address 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
D High Impedance Q
23 22 21 MSB
3
2
1
0 Data Out 1 7 6 5 4 3 2 1 0 Data Out 2 7
MSB
AI13878
1. As shown in Table 6, the most significant address bits are Don't Care.
Table 6.
Address range bits(1)
M95M01-R
Address bits
1. Bits A23 to A17 are Don't Care.
A16-A0
24/40
M95M01-R
Instructions
6.6
Write to Memory Array (WRITE)
As shown in Figure 12, to send this instruction to the device, Chip Select (S) is first driven Low. The bits of the instruction byte, address byte, and at least one data byte are then shifted in, on Serial Data Input (D). The instruction is terminated by driving Chip Select (S) High at a byte boundary of the input data. In the case of Figure 12, this occurs after the eighth bit of the data byte has been latched in, indicating that the instruction is being used to write a single byte. The self-timed Write cycle starts, and continues for a period tWC (as specified in Table 13), at the end of which the Write in Progress (WIP) bit is reset to 0. If, though, Chip Select (S) continues to be driven Low, as shown in Figure 13, the next byte of input data is shifted in, so that more than a single byte, starting from the given address towards the end of the same page, can be written in a single internal Write cycle. The selftimed Write cycle starts, and continues, for a period tWC (as specified in Table 13), at the end of which the Write in Progress (WIP) bit is reset to 0. Each time a new data byte is shifted in, the least significant bits of the internal address counter are incremented. If the number of data bytes sent to the device exceeds the page boundary, the internal address counter rolls over to the beginning of the page, and the previous data there are overwritten with the incoming data. (The page size is 256 bytes). The instruction is not accepted, and is not executed, under the following conditions:

if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable instruction just before) if a Write cycle is already in progress if the device has not been deselected, by Chip Select (S) being driven High, at a byte boundary (after the eighth bit, b0, of the last data byte that has been latched in) if the addressed page is in the region protected by the Block Protect (BP1 and BP0) bits.
Figure 12. Byte Write (WRITE) sequence
S 0 C Instruction 24-bit address Data byte 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
D High Impedance Q
23 14 13
3
2
1
0
7
6
5
4
3
2
1
0
AI13879
1. As shown in Table 6, the most significant address bits are Don't Care.
25/40
Instructions Figure 13. Page Write (WRITE) sequence
S 0 C Instruction 24-bit address Data byte 1 1 2 3 4 5 6 7 8 9 10
M95M01-R
28 29 30 31 32 33 34 35 36 37 38 39
D
15 14 13
3
2
1
0
7
6
5
4
3
2
1
0
S 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 C Data byte 2 Data byte 3 Data byte N
D
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
AI13880
1. As shown in Table 6, the most significant address bits are Don't Care.
26/40
M95M01-R
ECC (error correction code) and write cycling
7
ECC (error correction code) and write cycling
The M95M01-R device offers an ECC (Error Correction Code) logic which compares each 4-byte word with its associated 6 EEPROM bits of ECC. As a result, if a single bit out of 4 bytes of data happens to be erroneous during a Read operation, the ECC detects it and replaces it by the correct value. The read reliability is therefore much improved by the use of this feature. Note however that even if a single byte has to be written, 4 bytes are internally modified (plus the ECC bits), that is, the addressed byte is cycled together with the other three bytes making up the word. It is therefore recommended to write by words of 4 bytes in order to benefit from the larger amount of Write cycles. The M95M01-R device is qualified at 1 million (1 000 000) Write cycles, using a cycling routine that writes to the device by multiples of 4-byte packets.
8
8.1
Power-up and delivery state
Power-up state
After Power-up, the device is in the following state:

Standby Power mode Deselected (after Power-up, a falling edge is required on Chip Select (S) before any instructions can be started). Not in the Hold Condition Write Enable Latch (WEL) is reset to 0 Write In Progress (WIP) is reset to 0
The SRWD, BP1 and BP0 bits of the Status Register are unchanged from the previous power-down (they are non-volatile bits).
8.2
Initial delivery state
The device is delivered with the memory array set at all 1s (FFh). The Status Register Write Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0.
27/40
Maximum rating
M95M01-R
9
Maximum rating
Stressing the device outside the ratings listed in Table 7 may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the Operating sections of this specification, is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 7.
Symbol TA TSTG TLEAD VO VI VCC VESD
Absolute maximum ratings
Parameter Ambient operating temperature Storage temperature Lead temperature during soldering Output voltage Input voltage Supply voltage Electrostatic discharge voltage (Human Body Model)(2) Min. -40 -65 See -0.50 -0.50 -0.50 -4000 Max. 130 150 note (1) VCC+0.6 6.5 6.5 4000 Unit C C C V V V V
1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK(R) 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU 2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1=100pF, R1=1500, R2=500)
28/40
M95M01-R
DC and AC parameters
10
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristic tables that follow are derived from tests performed under the Measurement Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 8.
Symbol VCC TA Supply voltage Ambient operating temperature
Operating conditions
Parameter Min. 1.8 -40 Max. 5.5 85 Unit V C
Table 9.
Symbol CL
AC measurement conditions
Parameter Load capacitance Input rise and fall times Input pulse voltages Input and output timing reference voltages Min. 100 50 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC Max. Unit pF ns V V
Figure 14. AC measurement I/O waveform
Input Levels 0.8VCC Input and Output Timing Reference Levels 0.7VCC 0.3VCC
AI00825B
0.2VCC
Table 10.
Symbol COUT CIN
Capacitance(1)
Parameter Output capacitance (Q) Input capacitance (D) Input capacitance (other pins) Test condition VOUT = 0 V VIN = 0 V VIN = 0 V Min. Max. 8 8 6 Unit pF pF pF
1. Not 100% tested.
29/40
DC and AC parameters Table 11.
Symbol ILI ILO
M95M01-R DC characteristics
Parameter Test condition VIN = VSS or VCC S = VCC, VOUT = VSS or VCC C = 0.1VCC/0.9VCC at 2 MHz, VCC = 1.8 V, Q = open Min Max 2 2 1.5 4 5 5 3 5 -0.45 -0.45 0.75 VCC 0.7 VCC 0.25 VCC 0.3 VCC VCC+1 VCC+1 0.3 0.4 V V V Unit A A mA mA mA mA A A
Input leakage current Output leakage current
ICC
Supply current (Read)
C = 0.1VCC/0.9VCC at 5 MHz, VCC = 2.5 V, Q = open C = 0.1VCC/0.9VCC at 5 MHz, VCC = 5 V, Q = open
ICC0(1)
Supply current (Write)
During tW, S = VCC, S = VCC, VIN = VSS or VCC, 1.8 V VCC < 2.5 V S = VCC, VIN = VSS or VCC, 2.5 V VCC 5.5 V 1.8 V VCC < 2.5 V 2.5 V VCC 5.5 V 1.8 V VCC < 2.5 V 2.5 V VCC 5.5 V IOL = 0.15 mA, VCC = 1.8 V
ICC1
Supply current (Standby Power mode)
VIL
Input low voltage
V
VIH
Input high voltage
VOL
Output low voltage
VCC = 2.5 V, IOL = 1.5 mA or VCC = 5 V, IOL = 2 mA IOH = -0.1 mA, VCC = 1.8 V 0.8 VCC
VOH
Output high voltage
VCC = 2.5 V, IOH = -0.4 mA or VCC = 5 V, IOH = -2 mA
V
1. Characterized value, not tested in production.
30/40
M95M01-R Table 12. AC characteristics (VCC 2.5 V)
Test conditions specified in Table 9 Symbol fC tSLCH tSHCH tSHSL tCHSH tCHSL tCH (1) tCL
(1) (2) (2)
DC and AC parameters
Alt. fSCK tCSS1 tCSS2 tCS tCSH Clock frequency S active setup time
Parameter
Min. D.C. 60 60 60 60 60 90 90
Max. 5
Unit MHz ns ns ns ns ns ns ns
S not active setup time S Deselect time S active hold time S not active hold time
tCLH tCLL tRC tFC tDSU tDH
Clock high time Clock low time Clock rise time Clock fall time Data in setup time Data in hold time Clock low hold time after HOLD not active Clock low hold time after HOLD active Clock low set-up time before HOLD active Clock low set-up time before HOLD not active
tCLCH tCHCL
2 2 20 20 60 60 0 0 80 80 0 80 80 80 80 5
s s ns ns ns ns ns ns ns ns ns ns ns ns ns ms
tDVCH tCHDX tHHCH tHLCH tCLHL tCLHH tSHQZ
(2)
tDIS tV tHO tRO tFO tLZ tHZ tWC
Output disable time Clock low to output valid Output hold time Output rise time Output fall time HOLD high to output valid HOLD low to output High-Z Write time
tCLQV tCLQX tQLQH tQHQL
(2) (2)
tHHQV tHLQZ (2) tW
1. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max) 2. Value guaranteed by characterization, not 100% tested in production.
31/40
DC and AC parameters Table 13. AC characteristics (VCC < 2.5 V)
Test conditions specified in Table 9 Symbol fC tSLCH tSHCH tSHSL tCHSH tCHSL tCH (1) tCL
(1) (2) (2)
M95M01-R
Alt. fSCK tCSS1 tCSS2 tCS tCSH Clock frequency
Parameter
Min. D.C. 150 150 200 150 150 200 200
Max. 2
Unit MHz ns ns ns ns ns ns ns
S active setup time S not active setup time S deselect time S active hold time S not active hold time
tCLH tCLL tRC tFC tDSU tDH
Clock high time Clock low time Clock rise time Clock fall time Data in setup time Data in hold time Clock low hold time after HOLD not active Clock low hold time after HOLD active Clock low setup time before HOLD active Clock low setup time before HOLD not active
tCLCH tCHCL
2 2 50 50 150 150 0 0 200 200 0 200 200 200 200 5
s s ns ns ns ns ns ns ns ns ns ns ns ns ns ms
tDVCH tCHDX tHHCH tHLCH tCLHL tCLHH tSHQZ
(2)
tDIS tV tHO tRO tFO tLZ tHZ tWC
Output Disable time Clock low to output valid Output hold time Output rise time Output fall time HOLD high to output valid HOLD low to output High-Z Write time
tCLQV tCLQX tQLQH tQHQL
(2) (2)
tHHQV tHLQZ (2) tW
1. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max) 2. Value guaranteed by characterization, not 100% tested in production.
32/40
M95M01-R Figure 15. Serial input timing
DC and AC parameters
tSHSL S tCHSL C tDVCH tCHDX D MSB IN tCLCH LSB IN tCHCL tSLCH tCHSH tSHCH
Q
High Impedance
AI01447C
Figure 16. Hold timing
S tHLCH tCLHL C tCLHH tHLQZ Q tHHQV tHHCH
D
HOLD
AI01448B
33/40
DC and AC parameters Figure 17. Output timing
S tCH C tCLQV tCLQX Q tQLQH tQHQL D
ADDR.LSB IN
M95M01-R
tCLQV tCLQX
tCL
tSHQZ
LSB OUT
AI01449e
34/40
M95M01-R
Package mechanical data
11
Package mechanical data
Figure 18. SO8 narrow - 8 lead plastic small outline, 150 mils body width, package outline
h x 45 A2 b e 0.25 mm GAUGE PLANE k
8
A ccc c
D
E1
1
E A1 L L1
SO-A
1. Drawing is not to scale.
Table 14.
SO8 narrow - 8 lead plastic small outline, 150 mils body width, package mechanical data
millimeters inches(1) Max 1.75 0.10 1.25 0.28 0.17 0.48 0.23 0.10 4.90 6.00 3.90 1.27 4.80 5.80 3.80 - 0.25 0 0.40 1.04 5.00 6.20 4.00 - 0.50 8 1.27 0.0409 0.1929 0.2362 0.1535 0.0500 0.1890 0.2283 0.1496 0.0098 0 0.0157 0.25 0.0039 0.0492 0.0110 0.0067 0.0189 0.0091 0.0039 0.1969 0.2441 0.1575 0.0197 8 0.0500 Typ Min Max 0.0689 0.0098
Symbol Typ A A1 A2 b c ccc D E E1 e h k L L1 Min
1. Values in inches are converted from mm and rounded to 4 decimal digits.
35/40
Package mechanical data
M95M01-R
Figure 19. SO8W - 8 lead plastic small outline, 208 mils body width, package outline
A2 b e D
A c CP
N
E E1
1
A1
k
L
6L_ME
1. Drawing is not to scale.
Table 15.
SO8W - 8 lead plastic small outline, 208 mils body width, package mechanical data
millimeters inches(1) Max 2.50 0.00 1.51 0.40 0.20 0.35 0.10 0.25 2.00 0.51 0.35 0.10 6.05 5.02 7.62 1.27 - 0 0.50 8 6.22 8.89 - 10 0.80 0.0500 0.1976 0.3000 0 0.0197 8 0.0157 0.0079 0.0000 0.0594 0.0138 0.0039 Typ Min Max 0.0984 0.0098 0.0787 0.0201 0.0138 0.0039 0.2382 0.2449 0.3500 10 0.0315
Symbol Typ A A1 A2 b c CP D E E1 e k L N Min
1. Values in inches are converted from mm and rounded to 4 decimal digits.
36/40
M95M01-R
Part numbering
12
Part numbering
Table 16.
Example:
Ordering information scheme
M95M01 - R MN 6 T P
Device type M95 = SPI serial access EEPROM
Device function M01 = 1024 Kbits (131 072 x 8)
Operating voltage R = VCC = 1.8 V to 5.5 V
Package MN = SO8N (150 mils width) MW = SO8W (208 mils width)
Device grade 6 = Industrial temperature range, -40 to 85 C. Device tested with standard test flow
Option blank = standard packing T = tape and reel packing
Plating technology P or G = ECOPACK(R) (RoHS compliant)
For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. The category of second-level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label.
37/40
Part numbering Table 17.
M95M01-R Available M95M01-R products (package, voltage range, temperature grade)
Package SO8 (MN) SO8wide (MW) M95M01-R (1.8 V to 5.5 V) Range 6 Range 6
38/40
M95M01-R
Revision history
13
Revision history
Table 18.
Date 13-Mar-2007 15-May-2007 21-Jun-2007
Document revision history
Revision 1 2 3 Initial release. VCC conditions modified in Table 13: AC characteristics (VCC < 2.5 V). Small text changes. The device endurance is specified at more than 1 000 000 (1 million) cycles (corrected on page 1). Schmitt trigger inputs for enhanced noise margin added to Features on page 1. VIL and VIH values modified according to voltage range in Table 11: DC characteristics. Document status promoted from preliminary data to full datasheet. ICC0 modified in Table 11: DC characteristics. In Section 11: Package mechanical data, values in inches are converted from mm and rounded to 4 decimal digits. Table 17: Available M95M01-R products (package, voltage range, temperature grade) added. Small text changes. Changes
17-Jul-2007
4
24-Jan-2008
5
39/40
M95M01-R
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